An efficient hardware implementation of Gaussian Random Number (GRN) generator based upon Box-Muller (BM) and CORDIC algorithms is presented. We will illustrate a novel hardware architecture with flexible design space that unifies the two algorithms. A major advantage of this work is that unlike any of the previously reported architectures, it is possible to eliminate hardware multipliers and memory blocks in the synthesized hardware. This is achieved without compromising on statistical accuracy of GRN generators which is proved both through error analysis and standard tests. We will also demonstrate two different hardware implementations that vary in terms of speed, tail accuracy (4.7σ to 9.4σ), and utilization of hardware resources such as DSP blocks, logic slices and memory blocks on FPGAs. Finally, we will present a comparison of designed architectures with previously published hardware GRN generators.