The N-Body simulation process describes the evolution of a system of forces composed of N bodies, which may represent celestial objects, molecules, and so on. The most accurate algorithm for N-Body simulation, the All-Pairs method, is particularly compute intensive and software implementations on CPUs are inefficient in terms of performance and power consumption. An implementation on a hardware accelerator, such as an FPGA, would benefits in both these terms, exploiting a parallel execution at a relative low power profile. Moreover, it would also benefit faster methods with lower computational complexity, since many of them rely on the All-Pairs approach to approximate the calculation of forces. This work proposes a highly scalable, power efficient and high performance hardware architecture for the N-Body All-Pairs simulation problem. Our final implementation is able to scale up to systems with an arbitrary number of bodies thanks to a tiling approach that allows performance in the order of 13,441 MPairs/s, outperforming state of the art implementations on FPGA in terms of both pure performance, as well as performance per watt ratio. Finally, our design results to be more power efficient than Grape-8 ASIC.