Three-dimensional integrated circuits (3D ICs) can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogeneous integration. The inter-layer connection, which is generally implemented by the Through-Silicon-Via (TSV), is a key technology for 3D ICs. In this paper, we propose a unified simulated annealing technology to tackle the TSV assignment problem, including the signal TSV assignment of 3D nets and 3D buses. The experiment results show the effective of the method.