Logic packing is an important stage in an FPGA CAD flow,the structure of basic elements in a mapping library play a great role in the packing procedure. Based on this fact, a complex dual-output basic logic element (BLE) based improved packing algorithm WHUpakcer1.0 is presented. WHUpacker1.0 takes advantages of the structure of the dual-output BLEs different from the ones' used in previously academic studies. Upon the study on WHUpacker1.0 running on both combinational logic circuits and sequential logic circuits, the number of MOSFETs, and especially the number of BLEs after packing for most circuits decreases a lot. By taking the weight of the area parameter into account in a packing cost evaluation, it is found that WHUpacker1.0 is better than prior packing tools such as T-Vpack, its previous version WHUpacker, etc. The experimental results in turn guide how to design both BLEs in an FPGA and packing algorithms for an FPGA based design. The experimental results also suggest that the FPGA manufacturers and CAD tool designers should work together to make high productivity of FPGA based design.