In this paper, a parallel VLSI structure of multipliers in GF (2¹⁴) and GF (2¹⁶) is presented. The proposed parallel structure is based on de-composition of the original finite fields. The parallel structures can complete the finite field multiplication in a few clock cycles at the cost of endurable increase of logic area. The mapping matrices between binary and composite field representations of GF (2¹⁴) and GF (2¹⁶) are presented, as well as the heuristic search algorithm. Two BCH decoders that are based on GF (2¹⁴) and GF (2¹⁶) and using the proposed parallel Galois multiplier structures are implemented on FPGA. Complexity and data throughput analysis shows that it is suitable for cases which require finite field multiplications with high data throughput, such as BCH decoders in DVB broadcasting and nand-flash memories.