Pattern dependent interconnect physical parameter variations are studied based on a test chip in 65 nm manufacturing process. The line width bias caused by etch process and the line thickness dishing and erosion caused by CMP process are modeled using electrical and physical measurements. New closed form models for R and C thus are derived. Simulation results show excellent agreement between measurements and new models. The variation impacts on R/C and thus Elmore delay and bandwidth also are investigated qualitatively and quantitatively using the analytical models.