Since highly congested areas always result in routing detours and short circuits in ASIC & SoC design, the problem of local routing congestion is becoming increasingly rigorous in the place and route procedures. Many related researches laid special stress only on reducing congestions at placement stage or routing stage to short total wire length. Meanwhile, some place optimization constrains are integrated in most existing ARP tools. Although these available methods can alleviate congestion in some extent, they produce negative influence on the area and timing of whole chips. In this paper, a congestion-aware and area&timing oriented placement method which is called LC-KO is proposed. The LC-KO method focuses on reducing the local routing congestion with the purpose of optimizing area and timing. This method is composed of three stages: firstly, find the specific local congestion region which is called SLC-region in this paper; Secondly, find the specific HPC representing the cell with high pin number in this paper around which keep-out regions should be added; third, calculate the keep-out value. Experimental results show that compared with the ICC congestion constrains, the LC-KO method can reduce the shorts and improve the timing significantly, but with a lower runtime.