A low-power parallel-to-serial conversion circuit for CMOS image sensors (CIS) aimed for high-data-rate and power-restricted applications, is introduced in this paper. Parallel data are scanned and serialized by the delay-locked loop (DLL)-based pulse generator, wired-AND circuit and a current-mode amplifier. Unlike the conventional parallel-to-serial conversion circuit in CMOS image sensors, the proposed circuit doesn't need a clock tree and therefore consumes much less power. The circuit is designed in a 0.35μm CMOS process. The simulation results show that the power consumption of the proposed parallel-to-serial conversion circuit is reduced significantly compared to the conventional circuits especially in high-data-rate CMOS image sensor applications. The proposed circuit for 12-bit × 256-column CMOS image sensor is capable to operate at the data rate of 600 Mbps consuming 4.07 mW, which is 0.7% and 2.5% of the power consumption of the conventional shift-register scheme and the clock-gating scheme, respectively.