Through the failure analysis, leakage paths of data retention from both vertical and lateral directions are found. Then the relevant solutions (inter-layer dielectric thickness control and contact size control) are implemented and verified. It demonstrates that the loss data is induced by detrapped electrons or water-related electron traps. This One Time Program (OTP) cell described in this paper exhibits the very aggressive design rules to make more competitive cell density and performance. Based on the general 0.18um CMOS process, a method to solve the data retention issue from the Oxide-Nitride-Oxide (ONO) spacer process and Inter-Layer Dielectric (ILD) without any logic devices impact is introduced.