This paper presents a high-resolution ΣΔ ADC designed for high-precision applications. This design adopts a single-loop, fifth-order, tri-level analog modulator with feedforward path. The tri-level quantizer links the advantage of having better stability with having low specifications for the circuit. Internal negative feedback loop is utilized such that the quantization noise becomes optimally spread and minimized over the signal band. The proposed ΣΔ ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 101 dB with an oversampling ratio of 256. The active die area of the ADC is 2 mm² in a 0.35 μm CMOS process. Total power consumption is less than 3.7 mW.