Abstract:
A novel digital mixer implemented in TSMC 65 nm CMOS technology is proposed. 25% duty cycle quadrature 4-phase clocks are used for requirement of time division multiplexi...View moreMetadata
Abstract:
A novel digital mixer implemented in TSMC 65 nm CMOS technology is proposed. 25% duty cycle quadrature 4-phase clocks are used for requirement of time division multiplexing system. The proposed digital mixer is insensitive to clock jitter though the sampling frequency is 10.8-GHz. LTE protocol can be performed to the digital mixer. At 2.7GHz local oscillator frequency, the total power consumption is only 6.8mW when a 12-bit LTE signal with 40MHz bandwidth is applied.
Published in: 2017 IEEE 12th International Conference on ASIC (ASICON)
Date of Conference: 25-28 October 2017
Date Added to IEEE Xplore: 11 January 2018
ISBN Information: