The impacts of the gate length and width of the transistors on the single event upset (SEU) hardness of static random access memory (SRAM) cells has been investigated by SPICE simulations, biased on a partially depleted (PD) silicon-on-insulator (SOI) CMOS technology. The results show that increasing the gate width can dramatically enhance the linear energy transfer (LET) threshold of SEU, as compared with increasing the gate length. A new parameter, unit gate area LET threshold, is introduced for characterizing the change in efficiency of improving the SEU resistance with increasing the gate length and width of the transistors in a cell. The effect of decoupling capacitors on cell SEU LET threshold is also presented by making a comparison with that of the transistors with increased gate lengths.