This paper presents the full design flow of a flexible two-step VCO-based Delta-Sigma ADC architecture for software-defined radio applications. The proposed ADC reconfigures its signal bandwidth and A/D conversion accuracy in a cost- and power-efficient method. With the ADC open-loop structure and the mostly-digital building blocks, excellent figure-of-merits can be obtained for all modes. A reconfigurable ADC prototype designed in 90nm CMOS technology shows that it achieves 66/80.9dB SNDR respectively within a 20/2MHz signal bandwidth, consuming 5.1/2.9mW of power. The corresponding 78/79.8fJ/step figure-of-merits are among state-of-the-art reconfigurable ADCs, and could be improved even further if technology is scaled.