This paper proposed a band-limited signal based timing skew estimation scheme for time interleaved (TI) analog to digital convertor (ADC). In general, such method is more sensitive to the phase of the reference signal. A simple method to extract the timing skew mismatch without tracking the phase of the reference signal is presented. Besides, the reference signal is a filtered sinusoidal signal, thus it takes only a very small bandwidth to achieve better anti-interference capability. Generated by the same clock management unit which generates the sampling clock of the sub-ADCs, the reference signal dose not require additional circuits, and provides the system with real-time tracking capability against environmental changes. And there is no frequency error/jitter between the digital domain clock and the reference signal, thereby reducing the consumption of computational resources for signal frequency synchronization.