Abstract:
Coarse Grained Reconfigurable Architecture (CGRA) is a promising platform based on its high performance and low power. Efficient compilers have been developed for improvi...Show MoreMetadata
Abstract:
Coarse Grained Reconfigurable Architecture (CGRA) is a promising platform based on its high performance and low power. Efficient compilers have been developed for improving loop mapping performance using modulo scheduling, and the Dual-Vdd technique is popularly used to reduce power consumption in CGRAs. To achieve the best mapping performance and lowest power consumption simultaneously, this paper formulates a joint optimization problem of performance and power efficiency of CGRAs and proposes a low power optimization approach integrating Dual-Vdd assignment into the loop pipelining mapping. The experimental results show that the proposed optimization approach could reduce the power by 22.5% on average without decreasing performance.
Published in: 2017 IEEE 12th International Conference on ASIC (ASICON)
Date of Conference: 25-28 October 2017
Date Added to IEEE Xplore: 11 January 2018
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