Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design | IEEE Conference Publication | IEEE Xplore

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design


Abstract:

In August 2015, SHA-3 Standard was published as the next generation of Secure Hashing Algorithm. Several optimized implementations of SHA-3 on a 24-core processor with so...Show More

Abstract:

In August 2015, SHA-3 Standard was published as the next generation of Secure Hashing Algorithm. Several optimized implementations of SHA-3 on a 24-core processor with software and hardware co-design are proposed in this paper. For software designs, a 4-core mapping scheme with shared-memory reduces the delay time by exploring the internal parallelism of the algorithm; the scheme of 5 cores with packet router improves flexibility; and 24-core mapping with circuit router fully explores the parallelism with higher energy efficiency. Hardware approaches: specific instructions and novel latch-based accelerators, are proposed to improve performance and energy efficiency. The three software mappings provide a speedup of 3.1, 3.6 and 19.6, respectively. Almost 2 times better performance and energy efficiency are obtained with three specific instructions. The implementation of 4 latch-based accelerators achieves a throughput of 81.9 Gbps at 850MHz with 3.7 pJ/bit energy consumption per bit.
Date of Conference: 25-28 October 2017
Date Added to IEEE Xplore: 11 January 2018
ISBN Information:
Conference Location: Guiyang, China

References

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