A pLDMOS with vertical thin layer (VTL-pLDMOS) to obtain ultra-low Ron,sp (specific on-resistance) is proposed and investigated by TCAD tools in this paper. The vertical thin layer is linearly doped and a vertical Field Plate (FP) is used to terminate the electric field in the N-drift region. As a result, the electric field in the thin layer is uniformly distributed and the cell pitch is dramatically reduced, leading to a high breakdown-voltage (BV) and ultra-low Ron,sp. Simulation results confirm that for a 300 V pLDMOS, Ron,sp is reduced by 84% and 54% compared with those the p-type and n-type Triple RESURF "silicon limit", respectively. Moreover, Ron,sp of the proposed pLDMOS is 33% reduced even compared with that of an Enhanced RESURF Trench SOI pLDMOS (ERT-pLDMOS).