In the digital circuit design stage, the analysis and prediction of aging effects can help improve circuit reliability. In this paper, we firstly propose a fast aging-aware static timing analysis prediction approach for digital integrated circuits. Although the aging-aware analysis prediction model can be readily formulated into an optimization problem of the least square solution, the main challenge is the problem scale. A critical path selecting and sampling scheme is adopted to reduce dimensionality. Then we develop a solver based on Randomized Kaczmarz algorithm to realize an efficient solution. Based on industrial designs, experimental results for aging-aware static timing analysis show 9.95× speedup over the state-of-the-art method with similar accuracy.