High linearity low noise transconductance amplifier (LNTA) is very important for wideband SAW-less receivers(RX), but the linearity of LNTA realized by CMOS process is generally very poor. In order to meet specific requirements, linearization techniques are usually necessary. One of the most commonly-used methods is derivative superposition(DS), which can effectively improve IIP3. The traditional DS method uses a resistor and capacitor network to bias the gate of MOSFET, occupying additional chip area and complicating bias circuit design. Based on the principle of the traditional DS method, this paper proposes three new linearity compensation implementations, which simplify the circuit design. Under TSMC40nmLP process, the simulation results show that the IIP3 of the LNTA can be increased by more than 14dB by using these implementations.