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A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks | IEEE Conference Publication | IEEE Xplore

A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks


Abstract:

As AI begins to face more complex application scenarios, such as intelligent radar, autopilot and intelligent 5G, it often needs to work together with other traditional a...Show More

Abstract:

As AI begins to face more complex application scenarios, such as intelligent radar, autopilot and intelligent 5G, it often needs to work together with other traditional algorithms, mainly Digital Signal Processing (DSP) algorithms now. The proposed heterogeneous architecture with an AI core (on ASIC, for CNN) and IP core (on FPGA, for DSP) is usually adopted, but that’s inefficient due to the inconsistency in data transmission and operating frequency between chips. In order to solve this problem, this paper has proposed a reusable architecture based on Matrix Multiplication, which supports convolution, FFT and FIR operations on ASIC. We first analyzed the relationship among Convolution, FFT and FIR and find the best reusable architecture is Matrix multiplication. Then we decomposed the Convolution, FFT and FIR into Matrix multiplication, and designed the hardware architecture for them. Finally, we used Image registration algorithm to test the performance of our architecture, and get 500% speed up.
Date of Conference: 24-27 October 2023
Date Added to IEEE Xplore: 24 January 2024
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Conference Location: Nanjing, China

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