This paper presents a transient-enhanced digital LDO with adaptive clock edge control. An under-strength detector and an adaptive clock edge multiplier are devised to achieve adaptive tuning of the clock signal, which generates a double rising edge clock signal. This method can be combined with traditional digital feedforward techniques to significantly improve the transient response of the digital low-dropout regulator. The proposed DLDO is implemented using a 180nm CMOS process and achieves a maximum current efficiency of 98.8% and quiescent current of 9.8µA when operated at input and output voltages of 0.9V and 0.85V. The proposed method reduces the response time by 50%.