A hybrid Low-dropout regulator (H_LDO) with low quiescent current, fast transient response, and high PSRR is proposed for power management applications of digital chips. The voltage regulator includes a digital control circuit and an analog control circuit. During the stable output voltage stage, the control word of the digital circuit is in a maintained state, and the analog control circuit takes over the circuit to improve the power suppression ratio during the steady-state period; During the load jump stage, the digital circuit, as the main control circuit, can quickly search for control words that match the load to control the number of switch conduction in the PMOS array in a short. The proposed H_LDO is designed using a 55 nm process, and simulation results show that the proposed hybrid voltage regulator has a transient response speed of 506.9 ns when the load current jumps from 1 mA to 2 mA at a 1.2 V power supply voltage and an 800 mV output voltage, with a voltage undershoots of 128 mV.