With the increasing integration level of chips, the number of transistors and functional modules inside the chip is also increasing. It is complex to design the clock tree interconnects in a chip. At the same time, under the influence of high operating frequency and advanced technology, the impact of electromigration is highlighted on the clock tree interconnects. In order to ensure the performance of chip design and improve reliability, it is particularly important to quickly and accurately analyze the impact of electromigration problems on clock tree interconnects. In this paper, we have proposed a simulation analysis method based on COMSOL for the electrothermal coupled migration of clock trees. This method takes into account the effects of environmental factors and interconnect structures on electrothermal migration, qualitatively describing their relationship and exploring the impact of several basic clock interconnect structures on electrothermal migration.