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Process-induced skew reduction in nominal zero-skew clock trees | IEEE Conference Publication | IEEE Xplore

Process-induced skew reduction in nominal zero-skew clock trees


Abstract:

This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis fr...Show More

Abstract:

This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framework is used in a new algorithm that constructs deterministic nominal zero-skew clock trees that have reduced sensitivity to process variation. The new algorithm uses a sampling approach to perform route embedding during a bottom-up merging phase, but does not select the best embedding until the top-down phase. This results in clock trees that exhibit a mean skew reduction of 32.4% on average and a standard deviation reduction of 40.7% as verified by Monte Carlo. The average increase in total clock tree capacitance is less than 0.02%
Date of Conference: 24-27 January 2006
Date Added to IEEE Xplore: 13 March 2006
Print ISBN:0-7803-9451-8

ISSN Information:

Conference Location: Yokohama, Japan

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