We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera/spl reg/ APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.