This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock (MB) level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on a SoC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF (176/spl times/144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (digital multimedia broadcasting) phone.