Due to false paths and multicycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing analysis problem by considering both single-cycle and multicycle operations. We give a precise definition of multicycle false paths and provide the necessary conditions for multicycle sensitizable paths. We then propose an efficient algorithm to identify multicycle false paths. By considering both single-cycle and multicycle false paths, we could derive a shorter clock period than that determined by existing methods. Finally, we propose an algorithm to compute the valid clock period and demonstrate the improvement in clock frequency by taking multicycle false paths into account