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Cycle error correction in asynchronous clock modeling for cycle-based simulation | IEEE Conference Publication | IEEE Xplore

Cycle error correction in asynchronous clock modeling for cycle-based simulation


Abstract:

As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an ef...Show More

Abstract:

As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficient methodology for system verification because of its fast simulation speed. The cycle-based simulation has a limitation in using asynchronous clocks that causes inherent cycle errors. In order to reuse the output of a C-level cycle-based simulation for the verification of a lower level model, the C-level model should be cycle-accurate with respect to the lower level model. In this paper, a cycle error correction technique is presented for two asynchronous clock models. An example design is devised to show the effectiveness of the proposed method. Our experimental results show that the fast speed of cycle-based simulation can be fully exploited without sacrificing the cycle accuracy.
Date of Conference: 24-27 January 2006
Date Added to IEEE Xplore: 13 March 2006
Print ISBN:0-7803-9451-8

ISSN Information:

Conference Location: Yokohama, Japan

References

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