Abstract:
We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test ca...Show MoreMetadata
Abstract:
We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a fight upper bound of the execution time, and many useful hints to the designer.
Date of Conference: 24-27 January 2006
Date Added to IEEE Xplore: 13 March 2006
Print ISBN:0-7803-9451-8
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