Abstract:
A versatile recognition processor is presented that comprises 2.1M transistors using a 90 nm CMOS technology. It performs detection and recognition from image/video, soun...Show MoreMetadata
Abstract:
A versatile recognition processor is presented that comprises 2.1M transistors using a 90 nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.
Date of Conference: 18-21 January 2010
Date Added to IEEE Xplore: 25 February 2010
ISBN Information: