Abstract:
This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DA...Show MoreMetadata
Abstract:
This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 μm CMOS process. Power dissipation of this chip is 350 μW including the output buffers. The die area is 0.081mm2.
Date of Conference: 19-22 January 2015
Date Added to IEEE Xplore: 12 March 2015
ISBN Information: