Loading [a11y]/accessibility-menu.js
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection | IEEE Conference Publication | IEEE Xplore

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection


Abstract:

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (...Show More

Abstract:

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.
Date of Conference: 19-22 January 2015
Date Added to IEEE Xplore: 12 March 2015
ISBN Information:

ISSN Information:

Conference Location: Chiba, Japan

Contact IEEE to Subscribe

References

References is not available for this document.