A modern system-on-a-chip (SoC) typically consists of a large number of mixed-size circuit components with big macros and standard cells. Pre-placed macros (obstacles) and big macros further complicate such mixed-size circuit placement, and thus often make existing works fail to obtain a legal mixed-size placement. In this paper, we present an obstacle-aware macro placement algorithm which locates big macros to simultaneously optimize wirelength and routability. We first propose a circular contour to characterize the region formed by all obstacles. With the circular contour, we can effectively avoid the overlap between movable macros and obstacles, and simultaneously optimize the shape and area of the region for standard-cell placement. Unlike most previous macro placers that spend much time on searching for a feasible solution, our circular packing scheme packs movable macros around the obstacle contour to generate feasible solutions efficiently, and thus assists simulated annealing to focus on solution-quality optimization. Experimental results show that our algorithm can achieve the best quality, compared to manual designs provided by industry and leading academic mixed-size placers.