Abstract:
A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. T...View moreMetadata
Abstract:
A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. The complete, duty-cycled transmitter provides +1dBm peak output power, consuming 4.4mW. The receiver front-end shows -88dBm sensitivity at 0.85Mbps and a digital synchronization algorithm enables real-time duty cycling, resulting in a mean power consumption of 3mW.
Published in: IEEE Asian Solid-State Circuits Conference 2011
Date of Conference: 14-16 November 2011
Date Added to IEEE Xplore: 09 January 2012
ISBN Information: