An area- and power-optimized asynchronous 32× interleaved SAR ADC achieving 36 GS/s at 110mW with 1V supply on the interleaver and 0.9 V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area-optimized binary SAR ADC, and an area-optimized clocked reference buffer with a tunable constant-current source. It achieves 32.6dB SNDR up to 3GHz and 31.6dB up to 18GHz input frequency and 98fJ/conversion-step with a core chip area of 340×140μm² in 32nm SOI CMOS technology.