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A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers | IEEE Conference Publication | IEEE Xplore

A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers

Publisher: IEEE

Abstract:

This paper presents a 9-bit 1.8-GS/s pipelined ADC. It employs open-loop residue amplifiers with a linearization technique, two time-interleaved CDACs with stage gain cal...View more

Abstract:

This paper presents a 9-bit 1.8-GS/s pipelined ADC. It employs open-loop residue amplifiers with a linearization technique, two time-interleaved CDACs with stage gain calibration, and a double-sampling architecture. This open-loop structure achieves high speed, low power and moderate resolution without any digital nonlinearity calibrations. The fabricated ADC in 65-nm CMOS technology achieves an SNDR of 51 dB and a FoM of 83 fJ/conversion-step while the sampling rate is 1.8 GS/s.
Date of Conference: 09-11 November 2015
Date Added to IEEE Xplore: 21 January 2016
Electronic ISBN:978-1-4673-7191-9
Publisher: IEEE
Conference Location: Xiamen, China

References

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