Abstract:
A compact system for on-chip supply current wave-form reconstruction and power estimation is presented. The system, comprising a programmable current load, a sampling com...Show MoreMetadata
Abstract:
A compact system for on-chip supply current wave-form reconstruction and power estimation is presented. The system, comprising a programmable current load, a sampling comparator and processing logic, is implemented in a 28nm FD-SOI system-on-chip (SoC) to monitor the supply of a digital processor generated by a switched-capacitor DC-DC converter. The monitoring system is able to reconstruct the rippling supply waveform and extract core power consumption with a low area overhead (0.3% of the die area). Two different techniques yield either 2.5% accuracy with a 28 ms sample time or 5% accuracy with a 1 μs sample time, providing valuable information for on-chip power management strategies.
Published in: 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 07-09 November 2016
Date Added to IEEE Xplore: 09 February 2017
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