Abstract:
An area-efficient CTDSM for sensor applications is presented. The proposed capacitively-coupled CTDSM combines the functions of precision amplifier and DSM to achieve har...Show MoreMetadata
Abstract:
An area-efficient CTDSM for sensor applications is presented. The proposed capacitively-coupled CTDSM combines the functions of precision amplifier and DSM to achieve hardware efficiency. The 1-bit quantizer with FIR-DAC improves the linearity without using DEM in multi-bit architectures or large-size analog filters. The proposed currentsplitting OTA saves the capacitor area in the first integrator stage. Fabricated in a 0.18-μm CMOS, this chip draws 70 μA (?) from a 1.8-V supply, and achieves 12-bit resolution under 2-kHz bandwidth at ±40-mV input range. The circuit area is only 0.2 mm2.
Published in: 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
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