25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme | IEEE Conference Publication | IEEE Xplore

25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme


Abstract:

This paper proposes a low-power, small formfactor all-digital RNG utilizing a concept of capacitive coupling between two ROs to amplify jitter and a dual-edge sampling sc...Show More

Abstract:

This paper proposes a low-power, small formfactor all-digital RNG utilizing a concept of capacitive coupling between two ROs to amplify jitter and a dual-edge sampling scheme to increase the data rate. It is the most useful in battery-powered IoT applications where both energy and silicon area are critical constraints. The capacitive coupling effect with all digital circuit allows our design to operate reliably over a wide range of supply voltages. It consumes only 1.85 pJ/bit at 1V supply and 67 Mb/s, which scales down to 25 fJ/bit at 0.3 V, 5 Mb/s. Its overall FOM is 1.7×104, which is more than 3× better than existing designs.
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
ISBN Information:
Conference Location: Seoul, Korea (South)

References

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