Abstract:
This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By c...Show MoreMetadata
Abstract:
This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By concurrently performing gain adaptation and amplitude rectification for decoding the least significant bit (LSB), the proposed decoder greatly reduces power consumption compared with the conventional full-rate topology using three comparators. The sense amplifier (SA) in the AVGR is designed to have large gain and wide programmability in order to accommodate wide PAM4 input dynamic range (DR) while using a single constant reference voltage for decoding. Experimental results verify that the receiver IC, implemented in SMIC 28-nm high-k CMOS process, can receive and decoder a 24-Gb/s 190-mVpp PAM4 signal at a BER of 10-11.
Published in: 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
ISBN Information: