A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI | IEEE Conference Publication | IEEE Xplore

A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI


Abstract:

This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time...Show More

Abstract:

This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time domain 5-bit sequence including MSB and LSB. The architecture also enables built-in error correction with very low latency. This concept is demonstrated with prototype implemented in a 28nm FDSOI CMOS using only 18-data comparators. Consuming only 82mW at 28 Gb/s, the receiver is capable of compensating 27 dB channel loss with BER lower than 10−8. With error correction, the receiver can achieve BER lower than 10−10.
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
ISBN Information:
Conference Location: Seoul, Korea (South)

References

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