Abstract:
This paper presents an energy-efficient symmetric block-wise concatenated-BCH (SBC-BCH) decoder architecture for energy-starving mobile storages. The proposed 4KB SBC-BCH...Show MoreMetadata
Abstract:
This paper presents an energy-efficient symmetric block-wise concatenated-BCH (SBC-BCH) decoder architecture for energy-starving mobile storages. The proposed 4KB SBC-BCH code remarkably enhances the hard-decision-based error-correcting performance to defer the energy-consuming memorysensing operations for generating the soft-decision values, which are necessary to prolong the lifetime of flash memories. Thanks to the proposed powerful hard-decision code, the energy-efficient healthy memory condition is extended by 1.4 times. In addition, we introduce design methods for realizing the energy-efficiency SBC-BCH decoder. For example, the syndrome tracking allows the early start of the next decoding process, and the reordered Chien search minimizes the wasted waiting periods. Based on the proposed schemes, targeting the recent NAND flash memories, a prototype (37840, 34320) SBC-BCH decoder is realized in 65nm CMOS process. The prototype decoder achieves a throughput of 12.5 Gb/s while providing an energy efficiency of 3.56pJ/b, which is superior to the state-of-the-art ECC solutions for storages.
Published in: 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
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