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A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator | IEEE Conference Publication | IEEE Xplore

A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator


Abstract:

This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain unde...Show More

Abstract:

This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator share only a single dynamic DFF chain to reduce the digital power. A 40nm CMOS prototype achieves a Walden FoM of 1.5fJ/conversion-step while operating at 100kS/s from a 0.5V supply.
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
ISBN Information:
Conference Location: Seoul, Korea (South)

References

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