Abstract:
A scaling-friendly and PVT-robust pipelined SAR ADC reusing the first-stage comparator as a regenerative residue amplifier is proposed in this work. A low-power self-time...Show MoreMetadata
Abstract:
A scaling-friendly and PVT-robust pipelined SAR ADC reusing the first-stage comparator as a regenerative residue amplifier is proposed in this work. A low-power self-timed gain control block is combined with a mixed-signal background calibration to ensure a stable amplifier gain across PVT variation. A 130nm CMOS prototype achieves a peak Walden FoM of 9.2 fJ/conv-step and a Schreier FoM of 172 dB.
Published in: 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
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