A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS | IEEE Conference Publication | IEEE Xplore

A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS


Abstract:

This paper describes a novel fully integrated 35GHz frequency modulated continuous wave (FMCW) PLL with twins-VCO to 7GHz sweeping bandwidth. The proposed FMCW PLL is com...Show More

Abstract:

This paper describes a novel fully integrated 35GHz frequency modulated continuous wave (FMCW) PLL with twins-VCO to 7GHz sweeping bandwidth. The proposed FMCW PLL is composed of twins-VCOs, SDM modulator and waveform generator. A novel frequency sweeping extension (FSE) technique is proposed to make the twin-VCOs take turns to sweeping to realize wide sweeping bandwidth without sacrificing the sweeping time. The RMS frequency error of the proposed PLL is 0.9MHz and phase noise is -90dBc/Hz @1MHz. The total power consumption is around 43mW. The chip was fabricated in a 65nm LP CMOS technology. The PLL consumes an active area of 0.91mm2 and power of 43mW while operating at a 1.2 V single supply.
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
ISBN Information:
Conference Location: Seoul, Korea (South)

References

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