Abstract:
In this paper, we present a temperature compensated semi-digital integer-N PLL realized in a standard 130 nm CMOS technology, which achieves 48 fs rms phase jitter and a ...Show MoreMetadata
Abstract:
In this paper, we present a temperature compensated semi-digital integer-N PLL realized in a standard 130 nm CMOS technology, which achieves 48 fs rms phase jitter and a FOM of -245 dB. The presented design improves the phase noise performance of previously presented semi-digital PLLs by replacing the ring oscillator VCO by a semi-digitally tuned LC-tank VCO. In contrast to mostly digital PLLs, the presented architecture uses simple linear analog circuitry, removing the need for non-linear bang-bang PFDs or high speed oversampled ΣΔ-modulators.
Published in: 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 06-08 November 2017
Date Added to IEEE Xplore: 28 December 2017
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