Crosstalk fault reduction and simulation for clock-delayed domino circuits | IEEE Conference Publication | IEEE Xplore

Crosstalk fault reduction and simulation for clock-delayed domino circuits


Abstract:

In recent years, domino logic has received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino...Show More

Abstract:

In recent years, domino logic has received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic, that realizes any logic gate, has been proposed. Moreover, the domino logic has another drawback in that it is very sensitive to noise induced by crosstalk. Therefore, we focus our attention on crosstalk faults in CD domino circuits. In order to realize an efficient fault simulation, in this paper we propose a new method of target fault reduction, considering conflicts of signal values in the circuit and dominance of faults. In addition, we introduce a faster fault simulation method, which uses only logic values without handling details of the timing events of circuits.
Date of Conference: 20-20 November 2002
Date Added to IEEE Xplore: 28 February 2003
Print ISBN:0-7695-1825-7
Print ISSN: 1081-7735
Conference Location: Guam, USA

References

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