Analyzing the impact of process variations on DRAM testing using border resistance traces | IEEE Conference Publication | IEEE Xplore

Analyzing the impact of process variations on DRAM testing using border resistance traces


Abstract:

As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...Show More

Abstract:

As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memories. This paper discusses the issue of process variations, and shows how to deal with it in the context of fault analysis and test generation. The paper also introduces the concept of border resistance traces as a tool to optimize test stresses and inspect the impact of process variations on the optimization procedure. The concepts are discussed in the paper with the help of a practical example of a specific defect in the memory.
Published in: 2003 Test Symposium
Date of Conference: 16-19 November 2003
Date Added to IEEE Xplore: 08 December 2003
Print ISBN:0-7695-1951-2
Print ISSN: 1081-7735
Conference Location: Xi'an, China

References

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