Abstract:
A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurab...Show MoreMetadata
Abstract:
A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4 Mbit SRAM with reconfigurable cells of 16 bit data SRAMs. We also report the implementation of the proposed circuit. Four 16 bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test.
Published in: 2003 Test Symposium
Date of Conference: 16-19 November 2003
Date Added to IEEE Xplore: 08 December 2003
Print ISBN:0-7695-1951-2
Print ISSN: 1081-7735