Abstract:
This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth har...Show MoreMetadata
Abstract:
This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth harmonic of the 24 GHz input signal is generated by a differential pair driven in hard switching, loaded by a fourth order passive network that filters out the undesired current harmonics. The signal is further amplified by tuned cascode stages to deliver a peak output power of -3.8 dBm. The multiplier is implemented in a 0.13 μm SiGe BiCMOS technology and operates over the 114 to 126 GHz frequency range while occupying a 0.93 × 0.93mm2 silicon area.
Published in: 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)
Date of Conference: 03-06 November 2019
Date Added to IEEE Xplore: 30 January 2020
ISBN Information: